In the course of executing data manipulation and transfer requests, a data processing system may receive one or more task assignments in response to which the system temporarily aborts a current exercise and turns its attention instead to a demand for its services that is considered by the processor to be of more critical importance. In order to prevent a conflict among these requests for service, or interrupts, each interrupt request is assigned a service preference according to a priority scheme that is designed to ensure that the most critical tasks are always serviced effectively immediately, while lesser important tasks, commonly termed background tasks, are serviced after the critical requests for service have been honored. Moreover, as the name `interrupt` implies a request for processor service having a priority higher than that currently being processed will cause the processor to interrupt its current exercise and execute the task requested by the higher priority interrupt.
For implementing such a service request handling scheme, whether it be employed for intra or interprocessor interrupt handling, schemes containing dedicated interrupt lines associated with respective modules that may generate a request for service have been proposed. Priority among these dedicated interrupt lines is typically accomplished by way of a prescribed hardware architecture, through which a request on an interrupt line of relatively higher rank automatically locks out all requests of a lesser rank. More sophisticated priority architectures may include arbitration circuits through which all service requests are routed, the arbitration circuits prioritizing requests for service according to a predetermined assignment table. Because such interrupt handling approaches are typically hardware intensive and operationally rigid, in order to attain a fairly high degree of system performance (speed), they are constrained to limited applications, thereby restricting their adaptability to variable capacity, multiple capability processor architectures.